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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
DESCRIPTION
The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a "fold-back" inverting buffer and control gate FC. It features 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (B). These yield variable I/O gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs. The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 4 inputs (I), bidirectional I/O lines (B), internal flip-flop outputs (Q), and Complement Array output (C). The Complement Array consists of a NOR gate optionally linked to all AND gates for generating and propagating complementary AND terms. On-chip T/C buffers couple either True (I, B, Q) or Complement (I, B, Q, C) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Any of the 32 AND gates can drive bidirectional I/O lines (B), whose output polarity is individually programmable through a set of Ex-OR gates for implementing AND-OR or AND-NOR logic functions. Similarly, any of the 32 AND gates can drive the J-K inputs of all flip-flops. There are 4 AND gates for the Asynchronous Preset/Reset functions. All flip-flops are positive edge-triggered and can be used as input, output or I/O (for interfacing with a bidirectional data bus) in conjunction with load control gates (L), steering inputs (I), (B), (Q) and programmable output select lines (E). The PLS159A is field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment.
FEATURES
* High-speed version of PLS159 * fMAX = 18MHz
- 25MHz clock rate
PIN CONFIGURATIONS
N Package
CLK I0 I1 I2 I3 B0 B1 B2 B3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC F7 F6 F5 F4 F3 F2 F1 F0 OE
* Field-Programmable (Ni-Cr link) * 4 dedicated inputs * 13 control gates * 32 AND gates * 21 OR gates * 45 product terms:
- 32 logic terms - 13 control terms
GND 10
* 4 bidirectional I/O lines * 8 bidirectional registers * J-K, T, or D-type flip-flops * Power-on reset feature on all flip-flops * Asynchronous Preset/Reset * Complement Array * Active-High or -Low outputs * Programmable OE control * Positive edge-triggered clock * Input loading: -100A (max.) * Power dissipation: 750mW (typ.) * TTL compatible * 3-State outputs
APPLICATIONS
(Fn = 1)
N = Plastic Dual In-Line Package (300mil-wide)
A Package
I1 3 I2 I3 B0 B1 B2 4 5 6 7 8 9 10 11 12 13 I0 CLK VCC F7 2 1 20 19 18 17 16 15 14 F6 F5 F4 F3 F2
B3 GND OE F0 F1 A = Plastic Leaded Chip Carrier
* Random sequential logic * Synchronous up/down counters * Shift registers * Bidirectional data buffers * Timing function generators * System controllers/synchronizers * Priority encoder/registers
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In-Line Package (300mil-wide) 20-Pin Plastic Leaded Chip Carrier ORDER CODE PLS159AN PLS159AA DRAWING NUMBER 0408D 0400E
October 22, 1993
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853-1159 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
LOGIC DIAGRAM
(LOGIC TERMS-T)
(CONTROL TERMS) 11 OE
I0 I1 I2 I3
2 3 4 5 F0 F1 F2 F3 F4 F5 F6 F7 B0 B1 B2 B3 C C S3 X3 S2 X2 S1 X1 S0 X0 M7 P J K M6 J K M5 J K M4 J K Q CK' P J K M2 J K M1 J K M0 J K 31 24 23 16 15 87 0 FC Q CK' 1 CLK Q CK' 12 F0 Q CK' 13 F1 R Q CK' 14 F2 Q CK' 16 F4 Q CK' 17 F5 R Q CK' 18 F6 PB RB PA RA LB LA D3 D2 D1 D0 EA EB 9 8 7 6 B3 B2 B1 B0
19 F7
M3
15 F3
CK
NOTES: 1. All OR gate inputs with a blown link float to logic "0". 2. All other gates and control inputs with a blown link float to logic "1". 3. denotes WIRE-OR. 4. Programmable connection.
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
FUNCTIONAL DIAGRAM
(LOGIC TERMS) PB a b RB (CONTROL TERMS) PA RA LB LA D a a b b EA EB OE
Q Q C
C S X P J M K (4) CK R Q B
F
P J M K (4)
R Q
F
CK
T31
T0
FC CK CLK
LOGIC FUNCTION
Q3 1 Q2 0 Q1 1 Q0 0 SR PRESENT STATE A B C ... Sn + 1 NEXT STATE
FLIP-FLOP TRUTH TABLE
OE H L L X X X L L L L H H X X X X X L H L L L L L L L X X XX L X X L L CK P RJ KQ F Hi-Z H L H Q H L Q H* L* H* * L* *
STATE REGISTER 0 0 0 1
XH X L
L
HX L L L L
SET Q0: J0 = (Q3 K0 = 0
Q2 Q1 Q0) A B C . . .
L L L L H H +10V
LQ HL LH HQ HL LH HL LH
RESET Q1: J1 = 0 K1 = (Q3 Q2 Q1 Q0) A B C . . .

LH LH L L
HOLD Q2: J2 = 0 K2 = 0
NOTES: 1. Positive Logic: J-K = T0 + T1 + T2 .................. T31 Tn = C (I0 I1 I2 ...) (Q0 Q1 ...) (B0 B1 ...) 2. denotes transition from Low to High level. 3. X = Don't care 4. * = Forced at Fn pin for loading the J-K flip-flop in the Input mode. The load control term, Ln must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload. 5. At P = R = H, Q = H. The final state of Q depends on which is released first. 6. * * = Forced at Fn pin to load J-K flip-flop independent of program code (Diagnostic mode), 3-State B outputs.
TOGGLE Q3: J3 = (Q3 Q2 Q1 Q0) A B C . . .
K3 = (Q3 Q2 Q1 Q0) A B C . . .
LH X L
NOTE: Similar logic functions are applicable for D and T mode flip-flops.
XH
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
VIRGIN STATE
The factory shipped virgin device contains all fusible links intact, such that: 1. OE is always enabled. 2. Preset and Reset are always disabled. 3. All transition terms are disabled. 4. All flip-flops are in D-mode unless otherwise programmed to J-K only or J-K or D (controlled). 5. All B pins are inputs and all F pins are outputs unless otherwise programmed.
CAUTION: PLS159A PROGRAMMING ALGORITHM
The programming voltage required to program the PLS159A is higher (17.5V) than that required to program the PLS159 (14.5V). Consequently, the PLS159 programming algorithm will not program the PLS159A. Please exercise caution when accessing programmer device codes to insure that the correct algorithm is used.
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C
ABSOLUTE MAXIMUM RATINGS1
RATINGS SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg Supply voltage Input voltage Output voltage Input currents Output currents Operating temperature range Storage temperature range 0 -65 -30 PARAMETER MIN MAX +7 +5.5 +5.5 +30 +100 +75 +150 UNIT VDC VDC VDC mA mA C C
NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
DC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75V VCC 5.25V LIMITS SYMBOL Input VIH VIL VIC Output VOH VOL voltage2 High Low Clamp voltage2 High Low VCC = MIN, IOH = -2mA IOL = 10mA 2.4 0.35 0.5 V V VCC = MAX VCC = MIN VCC = MIN, IIN = -12mA -0.8 2.0 0.8 -1.2 V V V PARAMETER TEST CONDITION MIN TYP1 MAX UNIT
Input current IIH IIL High Low VCC = MAX, VIN = 5.5V VIN = 0.45V <1 -10 80 -100 A A
Output current IO(OFF) Hi-Z state4, 7 VCC = MAX, VOUT = 5.5V VOUT = 0.45V IOS ICC Capacitance CIN COUT Input Output VCC = 5.0V, VIN = 2.0V VOUT = 2.0V 8 15 pF pF Short circuit3, 5 VCC supply current6 VOUT = 0V VCC = MAX -15 150 1 -1 80 -140 -70 190 A A mA mA
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with VIH applied to OE. 5. Duration of short circuit should not exceed 1 second. 6. ICC is measured with the OE input grounded, all other inputs at 4.5V and the outputs open. 7. Leakage values are a combination of input and output leakage.
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
AC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75V VCC 5.25V, R1 =470, R2 = 1k LIMITS SYMBOL Pulse width tCKH tCKL tCKP tPRH Setup time5 tIS1 tIS2 tIS3 Hold time tIH1 tIH2 tCKO tOE1 tOD1 tPD tOE2 tOD2 tPRO tPPR Input Input (through Fn) Clock Output enable3 Output Output Output enable3 Output disable3 Preset/Reset Power-on/preset disable3 (I,B) F CK + CK + F F- F+ B B B+ F F- CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 5pF CL = 30pF CL = 30pF CL = 5pF CL = 30pF CL = 30pF 0 15 -5 10 ns ns Input Input (through Fn) Input (through Complement Array)4 (I,B) F (I,B) CK + CK + CK + CL = 30pF CL = 30pF CL = 30pF 35 15 55 30 10 45 ns ns ns Clock2 High Clock Low Period Preset/Reset pulse CK + CK - CK + (I,B) - CK - CK + CK + (I,B) + CL = 30pF CL = 30pF CL = 30pF CL = 30pF 20 20 55 35 15 15 45 30 ns ns ns ns PARAMETER FROM TO TEST CONDITION MIN TYP1 MAX UNIT
Propagation delay CK + OE - OE + (I,B) (I,B) + (I,B) - (I,B) + VCC + 15 20 20 25 20 20 35 0 20 30 30 35 30 30 45 10 ns ns ns ns ns ns ns ns
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. To prevent spurious clocking, clock rise time (10% - 90%) 10ns. 3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 4. When using the Complement Array tCKP = 75ns (min). 5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.
VOLTAGE WAVEFORMS
+3.0V 90%
TEST LOAD CIRCUIT
VCC 10% +5V S1
0V 5ns +3.0V 90% tR tF 5ns
C1
C2 I0 OE BY
R1
INPUTS 10% 0V 5ns 5ns
In BW BX CLK
DUT
R2
CL
BZ GND
OUTPUTS
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
NOTE: C1 and C2 are to bypass VCC to GND.
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
TIMING DIAGRAMS
+3V I, B (INPUTS) 1.5V 1.5V 0V tIH1 CLK tIS1 F (OUTPUTS) 1.5V tCKH tCKP 1.5V tOD1 VT VOL +3V OE 1.5V tOE1 1.5V 0V tIS1 +3V 1.5V tCKL 1.5V 0V VOH
TIMING DEFINITIONS
SYMBOL tCKH tCKL tCKP tPRH tIS1 PARAMETER Width of input clock pulse. Interval between clock pulses. Clock period. Width of preset input pulse. Required delay between beginning of valid input and positive transition of clock. Required delay between beginning of valid input forced at flip-flop output pins, and positive transition of clock. Required delay between positive transition of clock and end of valid input data. Required delay between positive transition of clock and end of valid input data forced at flip-flop output pins. Delay between positive transition of clock and when outputs become valid (with OE Low). Delay between beginning of Output Enable Low and when outputs become valid. Delay between beginning of Output Enable High and when outputs are in the OFF-State. Delay between VCC (after power-on) and when flip-flop outputs become preset at "1" (internal Q outputs at "0"). Propagation delay between combinational inputs and outputs. Delay between predefined Output Enable High, and when combinational outputs become valid. Delay between predefined Output Enable Low and when combinational outputs are in the OFF-State. Delay between positive transition of predefined Preset/Reset input, and when flip-flop outputs become valid.
tCKO
tIS2
Flip-Flop Outputs
+3V
tIH1
B (OUTPUTS)
I, B (OUTPUT ENABLE)
4.5V
VCC
tPPR
F (OUTPUTS)
1.5V
I, B (INPUTS)
1.5V
CLK tIS1 tCKH tCKP tCKL
October 22, 1993
CCCCC CCCCC CCCCC CCCCC
tPD tOE2 +1.5V tCKO tIH1 1.5V
I, B (INPUTS)
1.5V 0V
tIH2
VOH VT VOL tOD2 +3V +1.5V 0V
1.5V
tCKO
tOE1
Gate Outputs
tOD1
+5V
tPPR
0V
CCCCC CCCCC CCCCC CCCCC CCCCC
VOH 1.5V VOL +3V 1.5V 0V tIS1 +3V 1.5V 1.5V 0V
tPD
tOE2
tOD2
tPRO
Power-On Reset
31
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
TIMING DIAGRAMS (Continued)
+3V
CLK
tIS1* 1.5V
PRESET/RESET (I, B INPUTS)
tPRH (PRESET)
Q (RESET) tPRO F (OUTPUTS) (RESET) 1.5V (PRESET) 1.5V VOL * Preset and Reset functions override Clock. However, F outputs may glitch with the first positive Clock Edge if tIS1 cannot be guaranteed by the user. VOH
Asynchronous Preset/Reset
I, B (LOAD SELECT)
1.5V
OE
1.5V
L
F (INPUTS) tOD1 CLK
VT
Q
Flip-Flop Input Mode
October 22, 1993
CCCCCC CCCCCC CCCCCC CCCCCC CCCCCC
tIS1 1.5V 1.5V tOE1 (FORCED DIN) tIS2 tIH2 1.5V tCKH tIH1
I,B (INPUTS)
1.5V
0V
+3V
1.5V 0V
tCKO +3V
0V
+3V 1.5V 0V +3V 0V
+3V VOH 0V +3V VOL
CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC
32
0V
(DIN)
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
LOGIC PROGRAMMING
The PLS159A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP, Data I/O Corporation's ABELTM and Logical Devices Inc.'s CUPLTM design software packages. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLS159A logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information.
"AND" ARRAY - (I), (B), (Qp)
I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q
(T, FC, L, P, R, D)n STATE INACTIVE1, 2 CODE O STATE I, B, Q
(T, FC, L, P, R, D)n CODE H STATE I, B, Q
(T, FC, L, P, R, D)n CODE L STATE DON'T CARE
(T, FC, L, P, R, D)n CODE -
"COMPLEMENT" ARRAY - (C)
C C C C
C (Tn, FC) ACTION INACTIVE1, 3, 5 CODE O ACTION GENERATE5 (Tn, FC) CODE A
C (Tn, FC) ACTION PROPAGATE CODE
C (Tn, FC) ACTION TRANSPARENT CODE -
C
*
"OR" ARRAY - (F-F CONTROL MODE)
FC J M ENABLED K Q M DISABLED K FC J Q
"OR" ARRAY - (Qn = D-Type)
Tn J M = ENABLED K Q M = ENABLED K Tn J Q
ACTION J-K OR D (CONTROLLED)1
CODE A
ACTION J-K ONLY
CODE
Tn STATUS ACTIVE (Set)1
CODE A
Tn STATUS INACTIVE (Reset)
CODE
*
*
Notes on following page.
CAUTION: THE PLS159A Programming Algorithm is different from the PLS159.
October 22, 1993
33
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
"OR" ARRAY - (Qn = J-K Type)
Tn J M = DISABLED K Q M = DISABLED K Tn J Q M = DISABLED K Tn J Q M = DISABLED K Tn J Q
ACTION TOGGLE
CODE O
ACTION SET
CODE H
ACTION RESET
CODE L
ACTION HOLD
CODE -
"OR" ARRAY - (S or B)
Tn S, B Tn S, B
"EX-OR" ARRAY - (B)
S S
B
B
Tn STATUS ACTIVE1
CODE A
Tn STATUS INACTIVE
CODE
POLARITY LOW1
CODE L
POLARITY HIGH
CODE H
*
"OE" ARRAY - (E)
OE
OE
OE
OE
En ACTION IDLE1, 4 CODE O ACTION CONTROL
En CODE A ACTION ENABLE4
En CODE ACTION DISABLE
En CODE -
*
NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates. 2. Any gate (T, FC, L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn, FC. 4. En = O and En = * are logically equivalent states, since both cause Fn outputs to be unconditionally enabled. 5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.
October 22, 1993
34
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
PROGRAM TABLE
AND INACTIVE I, B, Q I, B, Q DON'T CARE INACTIVE GENERATE PROPAGATE TRANSPARENT - O H L - O A C TOGGLE SET RESET HOLD T E R M 0 1 2 3 4 O H L - AND I C 3 2 1 0 3 2 B(I) 1 0 7 6 5 Q(P) 4 3 2 1 0 7 6 5 4 Q(N) 3 2 1 0 3 (OR) B(O) 2 1 0 (Q = J/K) HIGH LOW H L I, B(I), Q(P) ACTIVE INACTIVE OR A P, R, B(O) (Q = D) J/K J/K or D (controlled) A CONTROL F/F MODE NOTES 1. The device is shipped with all links intact. Thus a background of entries corresponding to states of virgin links exists in the table, shown BLANK for clarity. 2. Program unused C, I, B, and Q bits in the AND array as (-). Program unused Q, B, P, and R bits in the OR array as (-) or (A), as applicable. 3. Unused Terms can be left blank. 4. Q (P) and Q (N) are respectively the present and next states of flip-flops Q. EB EA POLARITY
IDLE CONTROL ENABLE DISABLE
O A - EA, B
(POL) F/F MODE
THIS PORTION TO BE COMPLETED BY SIGNETICS
CUSTOMER SYMBOLIZED PART #
5 6 7 8 9 10 11
DATE RECEIVED
12 13
COMMENTS DATE REV PROGRAM TABLE #
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FC PB RB LB PA RA LA D3 D2 D1 D0 PIN 5 4 3 2 9 8 7 6 19 18 17 16 15 14 13 12
CF (XXXX)
TOTAL NUMBER OF PARTS
PURCHASE ORDER #
CUSTOMER NAME
PHILIPS DEVICE #
October 22, 1993
35
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 45 x 12)
PLS159A
SNAP RESOURCE SUMMARY DESIGNATIONS
(LOGIC TERMS) PB a b DIN159 NIN159 DIN159 NIN159 RB (CONTROL TERMS) PA RA LB LA D a a b b OEA159 EA EB OE
Q Q AND ANDFC OR C NOR EXOR159 S X P J M R Q B CAND C OEB159
F
JKFF159 (4) K CK TNOUT159
P J M K (4)
R Q
F
CK LNIN159
T31
T0
FC
LDIN159 CK CK159 CLK
October 22, 1993
36

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